Commit 8c789ab2 authored by Antonin Dudermel's avatar Antonin Dudermel
Browse files

remarks F2D

parent c360dae3
......@@ -277,6 +277,17 @@
language = {en}
}
@article{ugurdag2017hardwaredivision,
title = {Hardware Division by Small Integer Constants},
author = {Ugurdag, H. Fatih and {de Dinechin}, Florent and Gener, Y. Serhan and G{\"o}ren, Sezer and Didier, Laurent-St{\'e}phane},
year = {2017},
volume = {66},
pages = {2097--2110},
journal = {IEEE Transactions on Computers},
nopublisher = {IEEE},
number = {12}
}
@book{vetterli2014foundationssignal,
title = {Foundations of Signal Processing},
author = {Vetterli, Martin and Kova{\v c}evi{\'c}, Jelena and Goyal, Vivek K.},
......
......@@ -41,9 +41,10 @@ together using a block-diagram algebra (\lstinline{:} for composition,
\lstinline{,} for parallel evaluation\dots). The example on
\figref{fig:plus-simple} describes a simple stereo-to-mono converter. The two
inputs signals are added (primitive \lstinline{+}), then the sum is divided by 2
(written \lstinline{/(2)} in Faust). These two basic processors are composed with a
\lstinline{:}. Figure \ref{fig:plus-simple} also shows a graphical representation of the signal
processor described by the program made by the compiler.
(written \lstinline{/(2)} in Faust). These two basic processors are composed
with a \lstinline{:}. Figure \ref{fig:plus-simple} also shows a graphical
representation (made by the compiler) of the signal processor described by the
program.
As Faust is a compiled language, it first parses the program to get an abstract
tree representing a formula that implements the processor described in the
......@@ -119,7 +120,7 @@ every sample (At \(\SI{44100}{\hertz}\), it means once every
interruption to send the whole buffer to the Kernel. Similarly, when the OS
wants to play sounds, it sends a chunk of samples to the sound card, which
buffers them before playing them one after the other, through loudspeakers. With
a typical chunk size of 64 samples, this introduces a latency of at least
a typical buffer size of 64 samples, this introduces a latency of at least
\(64/ 44100 = \SI{1}{\milli\second} \). For applications such as active noise
reduction, on which one must be able to catch a sound wave with destructive
interference, with a sound speed of \(\SI{330}{\meter\per\second}\), this
......@@ -194,13 +195,13 @@ before floating-point numbers : the fixed-point numbers. The idea is the same as
floating-point numbers, but the exponent is no more part of the representation
but rather hard-coded in the program. The main advantage is that fixed-point
numbers in the same format behave almost exactly like integers. They require
therefore less resources (time, power, silicon) than floats. However, as being
far less versatile than floats, the programmer often have multiple fixed-point
formats in the same program, and must handle by hand in software the conversion
between multiple formats. This makes the code harder to read. The user must also
be precautions when choosing a format, as it can result to over-accurate useless
computations, completely scrambled values (just like in floats), or overflows
(just like ints).
therefore less resources (time, power, silicon) than floats. However, fixed-point
numbers being far less versatile than floats, the programmer often have multiple
fixed-point formats in the same program, and must handle by hand in software the
conversion between multiple formats. This makes the code harder to read. The
user must also be cautions when choosing a format, as it can result to
over-accurate useless computations, completely scrambled values (just like in
floats), or overflows (just like ints).
Besides, from the hardware point of view, there is often no other choice but
using a versatile format : the CPU designer does not know in advance what kind
......@@ -210,9 +211,10 @@ of them and because of silicon scarcity on the chip. This is yet not a problem
on an FPGA: behaving mostly as a reprogrammable circuit, one can afford to
implement very specific operators on very specific formats (e.g. a division by 3
taking as an input an unsigned int over 5 bits and outputting a fixed-point
number an unit in last position (ulp) of \(2^{-8}\)) without the risk of silicon
waste : if another very specific arithmetic operator is needed for another very
specific application, the FPGA can be reprogrammed for this task.
number an unit in last position (ulp) of \(2^{-8}\)
\cite{ugurdag2017hardwaredivision}) without the risk of silicon waste : if
another very specific arithmetic operator is needed for another very specific
application, the FPGA can be reprogrammed for this task.
The fixed-point numbers are simply a fractional generalization of integers. A
fixed-point unsigned format is described by two integers\footnote{but there are
......@@ -233,7 +235,7 @@ Most Significative Bit (MSB) and Least Significative Bit (LSB), so
\end{tikzpicture}
}
\hspace{\stretch{1}}
\subfloat[\(\sfix(3, -4)\)]{
\subfloat[\(\ufix(3, -4)\)]{
\begin{tikzpicture}[scale=0.5]
\fixpointnumber{0}{3}{-4}{0}
\fixpointpositions{0}{3}{-4}{0}
......@@ -362,10 +364,6 @@ logarithm in base 10.
\item For any \(a\in\Real\), we will denote \([a]\) the singleton interval \([a, a]\)
\end{itemize}
\subsubsection{Fixed-Point numbers}
\label{sec:fixed-point-signed}
\end{document}
%%% Local IspellDict: en
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